1. Field of the Invention
The present invention relates to a circuit for detecting a voltage level in a semiconductor device having a characteristic of hysteresis
Particularly, the present invention relates to a circuit for arbitrarily selecting and detecting one of the maximum level and the minimum level of the gate voltage in a semiconductor device for further accurately tuning a characteristic of hysteresis formed by the maximum level and the minimum level
More particularly, the present invention relates to a circuit for detecting a voltage level in a semiconductor device which can output a signal which can be externally monitored for further accurately tuning the device.
2. Discussion of Background
It is advantageous to reduce the area size of a semiconductor chip in various aspects. For example, when the chip is equipped in a portable remote terminal, it is possible to prevent the size of the portable remote terminal as a whole from increasing by reducing an area occupied by the chip in a board. Further, by the reduction of the area, the number of chips obtainable from one wafer increases, whereby the cost becomes more competitive. Further, it is expected that power dissipation in the chip is lowered in consideration of internal operation of the chip because a data bus length and so on can be restricted.
In order to practically reduce the area size of a chip, it is sufficient to further reduce dimensions for etching so as to make a size of transistor small. On such occasion, the film thickness of the gate oxide film (hereinbelow referred to as Tox) of the transistor is also made thin in accordance with the scaling law. As a result, although the efficiency of transistor is improved, there will be caused a problem about reliability by the thinned gate oxide film. In other words, the gate oxide film is apt to be destroyed by a lower gate voltage and therefore it is not possible to readily apply a high gate voltage.
For example, transistors composing memory cells of a dynamic random access memory (DRAM), which is one of representative semiconductor memories, will be considered. Generally, a boosted voltage (hereinbelow referred to as Vpp) is applied to a gate voltage in order to write satisfactory data of high (H) into the memory cell. Provided that a level of the data of high (H) is Vh and a threshold value of the cell transistor is Vthh, the relation between these can be expressed as Vpp&gt;Vh+Vthh. Accordingly, the level of Vpp can be fairly high. In order to avoid such situation, it is necessary to reduce the level of Vpp and simultaneously control variations of Vpp with accuracy by adopting a method of reducing Vthh in the manufacturing process, a method of reducing Vh by increasing a margin for operating the cell, and so on.
For example, in a DRAM, it is necessary to reflesh cells because data of H written in the cells are lost in accordance with a lapse of time. Frequency of refleshing is determined by a capability of holding data in the cells. Such capability can be enhanced by improvements of physical values and of circuit competence in the manufacturing process. Also, it is possible to normally read out the data by increasing sensitivity of a sense amplifier even through a part of data in the cells is lost to a certain extent.
Factors of the variations of Vpp are dissipation causes by charging and discharging loads on Vpp, for example, gates of the memory cell and word lines (hereinbelow referred to as WL) connected thereto, charging the load on Vpp and a decoupling capacitance on Vpp with an electric current supplied from a Vpp pump for supplementing the dissipation, whereby the level of Vpp varies by several hundred mm volts (mV) around a certain level.
In this, the decoupling capacitance is necessary for storing electric potential generated in the circuit, which potential is not limited to Vpp, because generated electric charges should be absorbed somewhere to suppress a variation of the internal electric potential accompanied by internal operation. The decoupling capacitance is, for example, a parasitic capacitance existing in wiring for supplying internal potential to various portions and a gate capacitance of a transistor receiving such internal potential. Although the sum of these capacitances may be sufficient as the decoupling capacitance, an additional decoupling capacitance is provided in an appropriate location by utilizing an inter-layer film interposed between proper flat plates arranged in parallel, a gate capacitance of transistor, or other various means when such a parasitic capacitance is not sufficient. The level of Vpp can be controlled based on a circuit for detecting the Vpp level, and a range of variability of the Vpp level is determined by a velocity of reaction of the circuit for detecting the Vpp level and a capability of the Vpp pump. A case that the velocity of reaction of the circuit for detecting Vpp level is sufficiently higher than a velocity of dissipation of Vpp, and the capability of the Vpp pump is sufficiently high will be considered. The level of charging the load on Vpp and the decoupling capacitance on Vpp is controlled to be higher than a target level of Vpp, which is an average level of Vpp, because it is practically intended to supply for the dissipation of Vpp occurred during a catch-up reaction time of the circuit for detecting the Vpp level to the first operation of rows. Thus, it was preferable to constitute the circuit for detecting the Vpp level so that the level of stopping the charge and the level of detecting the insufficient charge are different, whereby the circuit resultantly has a characteristic of hysteresis.
On the other hand, two reaction levels by the characteristic of hysteresis in the circuit for detecting the Vpp level is based on a certain reference potential. This reference potential is supplied from a circuit for generating reference potential, and these levels are tuned and adjusted to be an appropriate value before the delivery. In general, a method for tuning is to use a pad by which the Vpp level can be monitored and to measure outputs from the pad by a tester and so on obtained before and after fuses of the circuit for generating reference voltage are cut.
In accordance with the above-mentioned method, the detecting level by the circuit for detecting Vpp level was tuned based on an average value of the variations of the Vpp level. Therefore, even though the range of variability was wide, as long as the average value between the maximum level and the minimum level was the same, it was turned to be an identical level. When the minimum level was too low, sufficient data of H could not be written in memory cells, whereby malfunction was caused. Further, since the Vpp level was monitored by means of the pad, the Vpp level was not accurately monitored if the pad was shorted to the other potential values in the vicinity of the monitor pad.
Although the problems were explained with respect to the circuit utilizing Vpp as described in the above, it is generally common to a circuit for detecting a level which circuit has a characteristic of hysteresis.